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7-Bit Programmable, 3-Phase, Mobile CPU Synchronous Buck Controller ADP3212/NCP3218
FEATURES
Single-chip solution Fully compatible with the Intel(R) IMVP-6.5TM specifications Selectable 1- , 2-, or 3-phase operation with up to 1 MHz per phase switching frequency Phase 1 and Phase 2 Integrated MOSFET drivers Input Voltage Range of 3.3 V to 22 V Guaranteed 8 mV worst-case differentially sensed core voltage error over temperature Automatic power-saving mode maximizes efficiency with light load during deeper sleep operation Active current balancing between output phases Independent current limit and load line setting inputs for additional design flexibility Built-in power-good blanking supports voltage identification (VID) on-the-fly transients 7-bit, digitally programmable DAC with 0.3 V to 1.5 V output Short-circuit protection with programmable latch-off delay Clock enable output delays the CPU clock until the core voltage is stable Output power or current monitor options 48-lead QFN 6x6mm (NCP3218) 48-lead QFN 7x7mm (ADP3212)
GENERAL DESCRIPTION
The ADP3212/NCP3218 is a highly efficient, multiphase, synchronous buck switching regulator controller. With its integrated drivers, the ADP3212/NCP3218 is optimized for converting the notebook battery voltage into the core supply voltage required by high performance Intel processors. An internal 7-bit DAC is used to read a VID code directly from the processor and to set the CPU core voltage to a value within the range of 0.3 V to 1.5 V. The ADP3212/NCP3218 is programmable for 1-, 2-, or 3-phase operation. The output signals ensure interleaved 2- or 3-phase operation. The ADP3212/NCP3218 uses a multimode architecture run at a programmable switching frequency and optimized for efficiency depending on the output current requirement. The ADP3212/NCP3218 switches between single- and multi-phase operation to maximize efficiency with all load conditions. The chip includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. The ADP3212/NCP3218 also provides accurate and reliable shortcircuit protection, adjustable current limiting, and a delayed power-good output. The IC supports on-the-fly output voltage changes requested by the CPU. The ADP3212/NCP3218 are specified over the extended commercial temperature range of -40C to 100C. The ADP3212 is available in a 48-lead QFN 7x7mm 0.5 mm pitch package. The NCP3218 is available in a 48-lead QFN 6x6mm 0.4 mm pitch package. Except for the packages, the ADP3212 and NCP3218 are identical. ADP3212 and NCP3218 are HalogenFree, Pb-Free and RoHS compliant.
APPLICATIONS
Notebook power supplies for next-generation Intel processors
Rev. SpA | Page 1 of 43
ADP3212/NCP3218
FUNCTIONAL BLOCK DIAGRAM
GND VCC EN UVLO Shutdown and Bias VEA + REF LLINE SWFB1 SWFB2 SWFB3 PH0 PH1 DAC + 200mV CSREF + + DAC - 300mV PWRGD PWRGD Open Drain CLKEN Open Drain Precision Reference VID DAC PWRGD Start Up Delay OCP Shutdown Delay Current Limit Circuit Number of Phases PVCC PGND OD3 PWM3 PSI and DPRSLP Logic Current Monitor + + + _ 1.55V + CSREF OVP + + RPM RT RAMP VARFREQ BST1 Oscillator Current Balancing Circuit Driver Logic DRVH1 SW1 PVCC DRVL1 PGND BST2 DRVH2 SW2 DRVL2
TRDET COMP FB
TRDET Generator
PSI DPRSLP IMON
CLKEN
Soft Transient Delay CLKEN Start Up Delay Delay Disable
CSREF CSSUM CSCOMP ILIM
FBRTN
Thermal Throttle Control Soft Start
TTSENSE VRTT
DAC IREF VID2 VID1 VID0
REF
VID6 VID5
VID4
VID3
Figure 1.
Rev. SpA | Page 2 of 43
ADP3212/NCP3218 TABLE OF CONTENTS
Features...............................................................................................1 Applications .......................................................................................1 General Description..........................................................................1 Functional Block Diagram ...............................................................2 Revision History................................................................................3 Specifications .....................................................................................4 Timing Diagram................................................................................9 Absolute Maximum Ratings ..........................................................10 ESD Caution ................................................................................10 Pin Configuration and Function Descriptions ...........................11 Test Circuits .....................................................................................13 Typical Performance Characteristics............................................14 Theory of Operation .......................................................................15 Number of Phases .......................................................................15 Operation Modes ........................................................................15 Differential Sensing of Output Voltage ....................................19 Output Current Sensing .............................................................19 Active Impedance Control Mode..............................................19 Current Control Mode and Thermal Balance.........................20 Voltage Control Mode ................................................................20 Power-Good Monitoring............................................................20 Power-Up Sequence and Soft Start ...........................................21 Current Limit...............................................................................21 Changing VID on the Fly...........................................................21 Output Crowbar..........................................................................24 Reverse Voltage Protection ........................................................24 Output Enable and UVLO.........................................................24 Thermal Throttling Control ......................................................24 Application Information ................................................................28 Setting the Clock Frequency for PWM....................................28 Setting the Switching Frequency for RPM Operation of Phase 1 .....................................................................................................28 Soft Start and Current Limit Latch-Off Delay Times ............28 Inductor Selection.......................................................................28 COUT Selection..............................................................................31 Power MOSFETs .........................................................................32 Ramp Resistor Selection.............................................................33 Current Limit Setpoint...............................................................33 Current Monitor..........................................................................33 Feedback Loop Compensation Design ....................................33 CIN Selection and Input Current di/dt Reduction ..................35 RC Snubber..................................................................................35 Selecting Thermal Monitor Components................................35 Tuning Procedure for ADP3212/NCP3218.............................36 Layout and Component Placement ..........................................37 Outline Dimension .........................................................................39 Ordering Guide ...........................................................................41
REVISION HISTORY
4/08--Revision Sp0: Initial Version
Rev. SpA | Page 3 of 43
ADP3212/NCP3218 SPECIFICATIONS
VCC = PVCC = 5V, FBRTN = PGND = GND = 0 V, H = 5V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V, VVID = VDAC = 1.2000 V, TA = -40C to 100C, unless otherwise noted.1 Current entering a pin (sink current) has a positive sign. Table 1.
Parameter Symbol Conditions Min Typ Max Units
VOLTAGE CONTROL
VOLTAGE ERROR AMPLIFIER (VEAMP) FB, LLINE Voltage Range2 FB, LLINE Offset Voltage2 LLINE Bias Current FB Bias Current LLINE Positioning Accuracy COMP Voltage Range2 COMP Current
VFB, VLLINE VOSVEA ILLINE IFB VFB - VVID VCOMP ICOMP
Relative to CSREF = VDAC Relative to CSREF = VDAC
Measured on FB relative to VVID, LLINE forced 80 mV below CSREF COMP = 2 V, CSREF = VDAC FB forced 200 mV below CSREF FB forced 200 mV above CSREF CCOMP = 10 pF, CSREF = VDAC, Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF Non-inverting unit gain configuration, RFB = 1 kOhm See VID table Measured on FB (includes offset), relative to VVID VVID = 1.2000 V to 1.5000 V, T = -40C to 100C VVID = 0.3000 V to 1.1875 V, T = -40C to 100C
-200 -0.5 -100 -1 -77.5 0.85
-80
+200 +0.5 +100 +1 -82.5 4.0
mV mV nA A mV V mA mA
-0.75 6
COMP Slew Rate
SRCOMP
15 -20 20
Gain Bandwidth2 VID DAC VOLTAGE REFERENCE VDAC Voltage Range2 VDAC Accuracy
GBW
V/s V/s MHz
0 -8.5 -7.5 -1 0.02 1.100 200 1.4 60 0.0625 0.25 1 0.4 -90
1.5 +8.5 +7.5 +1
V mV mV LSB % V s ms s LSB/s LSB/s LSB/s LSB/s A
VFB - VVID
VDAC Differential Nonlinearity2 VDAC Line Regulation VDAC Boot Voltage Soft-start Delay2 Soft-start Time Boot Delay VDAC Slew Rate2
VFB VBOOTFB tDSS tSS tBOOT
VCC = 4.75 V to 5.25 V Measured during boot delay period Measured from EN pos edge to FB = 50 mV Measured from FB = 50 mV to FB settles to 1.1 V within 5 % Measured from FB settling to 1.1 V within 5% to CLKEN# neg edge Soft-start Non-LSB VID step, DPRSLP = H, Slow C4 Entry/Exit Non-LSB VID step, DPRSLP = L, Fast C4 Exit LSB VID step, DVID transition
FBRTN Current
IFBRTN
-200
VOLTAGE MONITORING and PROTECTION
POWER GOOD CSREF Under-voltage Threshold CSREF Over-voltage Threshold VUVCSREF VOVCSREF Relative to nominal VDAC voltage Relative to nominal VDAC voltage -240 150 -300 200 -360 250 mV mV
Rev. SpA | Page 4 of 43
ADP3212/NCP3218
Parameter CSREF Crowbar Voltage Threshold CSREF Reverse Voltage Threshold PWRGD Low Voltage PWRGD High, Leakage Current PWRGD Start-up Delay PWRGD Latch-off Delay PWRGD Propagation Delay3 Crowbar Latch-off Delay2 PWRGD Masking Time CSREF Soft-stop Resistance Symbol VCBCSREF VRVCSREF Conditions Relative to FBRTN, VVID > 1.1 V Relative to FBRTN, VVID 1.1 V Relative to FBRTN, Latch-off mode CSREF is falling CSREF is rising IPWRGD(SINK) = 4 mA VPWRDG = 5 V Measured from CLKEN# neg edge to PWRGD pos edge Measured from Out-off-Good-Window event to Latch-off (switching stops) Measured from Out-off-Good-Window event to PWRGD neg edge Measured from Crowbar event to Latch-off (switching stops) Triggered by any VID change or OCP event EN = L or Latch-off condition Min 1.5 1.3 -370 Typ 1.55 1.35 -300 -75 85 Max 1.6 1.4 Units V V mV mV mV A ms s ns ns s
VPWRGD IPWRGD TSSPWRGD TLOFFPWRGD TPDPWRGD TLOFFCB
-10 250 1
8 120 200 200 100 70
CURRENT CONTROL
CURRENT-SENSE AMPLIFIER (CSAMP) CSSUM, CSREF CommonMode Range2 CSSUM, CSREF Offset Voltage CSSUM Bias Current CSREF Bias Current CSCOMP Voltage Range2 CSCOMP Current
Voltage range of interest VOSCSA IBCSSUM IBCSREF CSREF - CSSUM , TA = -40C to 85C
0 -1.2 -20 -3 0.05 -750 1 20 -20 20
2 +1.2 +20 +3 2
V mV nA A V A mA V/s V/s MHz
ICSCOMPsource ICSCOMPsink CSCOMP Slew Rate2
Gain Bandwidth2
GBWCSA
Voltage range of interest CSCOMP = 2 V, CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF CCSCOMP = 10 pF, CSREF = VDAC, Open loop configuration CSSUM forced 200 mV below CSREF CSSUM forced 200 mV above CSREF Non-inverting unit gain configuration RFB = 1 kOhm
CURRENT MONITORING and PROTECTION
CURRENT REFERENCE IREF Voltage CURRENT LIMITER (OCP) Current Limit (OCP) Threshold VREF VLIMTH RREF = 80 k to set IREF = 20 uA Measured from CSCOMP to CSREF, RLIM = 1.5 k, 3-ph configuration, PSI = H 3-ph configuration, PSI = L 2-ph configuration, PSI = H 2-ph configuration, PSI = L 1-ph configuration Measured from OCP event to PWRGD de-assertion Measured from ILIM to IMON ILIM = -20 A ILIM = -10 A
Rev. SpA | Page 5 of 43
1.55
1.6
1.65
V
-75 -22 -75 -36 -75
-90 -30 -90 -45 -90 120
-106 -38 -106 -54 -106
mV mV mV mV s
Current Limit Latch-off Delay CURRENT MONITOR Current Gain Accuracy
IMON/ILIM
3.7 3.6
4 4
4.3 4.4
-
ADP3212/NCP3218
Parameter IMON Clamp Voltage Symbol VMAXMON Conditions ILIM = -5 A Relative to FBRTN, ILIMP = -30 uA Min 3.5 1.0 Typ 4 Max 4.5 1.15 Units V
PULSE WIDTH MODULATOR
CLOCK OSCILLATOR RT Voltage VRT VARFREQ = high, RT = 125 k, VVID = 1.5000 V VARFREQ = low See also VRT(VVID) formula Operation of interest TA = +25C, VVID = 1.2000 V RT = 72 k RT = 120 k RT = 180 k EN = high, IRAMP = 60 A EN = low EN = high EN = low, RAMP = 19 V VRAMP - VCOMP VVID = 1.2 V, RT = 215 k See also IRPM(RT) formula VCOMP - (1 + VRPMTH) Relative to COMP sampled TCLK time earlier 3-phase configuration 2-phase configuration 1-phase configuration Relative to COMP sampled TCLK time earlier 3-phase configuration 2-phase configuration 1-phase configuration Logic low, ITRDET#sink = 4mA Logic high, VTRDET# = VCC Operation of interest for current sensing SWX = 0 V, SWFB = 0 V -600 20 1.125 0.9 0.3 1.25 1 1.375 1.1 3 V V MHz
PWM Clock Frequency Range2 PWM Clock Frequency
fCLK fCLK
1100 700 500 0.9 1 -1
1257 800 550 1 VIN
1400 900 600 1.1 100 +1
kHz kHz kHz V V A A mV A mV
RAMP GENERATOR RAMP Voltage RAMP Current Range2 PWM COMPARATOR PWM Comparator Offset2 RPM COMPARATOR RPM Current RPM Comparator Offset2 EPWM CLOCK SYNC Trigger Threshold2
VRAMP IRAMP
VOSRPM IRPM VOSRPM
3 -9 3
350 400 450
mV mV mV
TRDET# Trigger Threshold2
TRDET# Low Voltage2 TRDET# Leakage Current SWITCH AMPLIFIER SW Common Mode Range2 SWFB Input Resistance ZERO CURRENT SWITCHING COMPARATOR SW ZCS Threshold Masked Off-Time
VLTRDET IHTRDET VSW(X)CM RSW(X)
-450 -500 -600 30
300 5 +200 50
mV mV mV mV A mV k
35
VDCM(SW1) tOFFMSKD
DCM mode, DPRSLP = 3.3 V Measured from DRVH1 neg edge to DRVH1 pos edge at max frequency of operation
-3 600
mV ns
SYSTEM I/O BUFFERS
VID[6:0], DPRSLP, PSI# INPUTS Input Voltage Refers to driving signal level Logic low Logic high
Rev. SpA | Page 6 of 43
0.3 0.7
V V
ADP3212/NCP3218
Parameter Input Current Symbol Conditions V = 0.2 V VID[6:0], DPRSLP (active pull down to GND) PSI# (active pull-up to VCC) Any VID edge to FB change 10% Refers to driving signal level Logic low Logic high Min Typ -1 1 200 Max Units A A ns
VID Delay Time2 VARFREQ Input Voltage
0.7 4 1
Input Current EN INPUT Input Voltage Refers to driving signal level Logic low Logic high EN = L or EN = H (static) 0.8 V < EN < 1.6 V (during transition) Refers to driving signal level Logic low Logic high
V V A
0.4 1.9 10 -70
Input Current PH1, PH0 INPUTS Input Voltage
V V nA A V
0.5 4 1 A 200 1 mV A
Input Current CLKEN OUTPUT Output Low Voltage Output High, Leakage Current PWM3, OD3 OUTPUTS Output Voltage Logic low, ISINK = 400 A Logic high, ISOURCE = -400 A 4 Logic low, Isink = 4 mA Logic high, VCLKEN = VCC
60
10 5
100
mV V
THERMAL MONITORING and PROTECTION
TTSNS Voltage Range2 TTSNS Threshold TTSNS Hysteresis TTSNS Bias Current VRTT Output Voltage VCC = 5 V, TTSNS is falling TTSNS = 2.6 V Logic low, IVRTT(SINK) = 400 A Logic high, IVRTT(SOURCE) = -400 A 0 2.45 -2 4.5 4.5 EN = high EN = 0 V VCC is rising VCC is falling 7 10 4.4 4.15 150 1.8 1.0 15 13 30 10 5 2.5 95 5 2.55 2 100 V V mV A mV V V mA A V V mV ns ns ns
VVRTT
SUPPLY
Supply Voltage Range Supply Current VCC OK Threshold VCC UVLO Threshold VCC Hysteresis2 HIGH-SIDE MOSFET DRIVER Pull-up Resistance, Sourcing Current3 Pull-down Resistance, Sinking Current3 Transition Times Dead Delay Times VCC 5.5 10 150 4.5
VCCOK VCCUVLO
4.0
BST = PVCC BST = PVCC trDRVH, tfDRVH tpdhDRVH BST = PVCC, CL = 3 nF, Figure 2 BST = PVCC, CL = 3 nF, Figure 2 BST = PVCC, Figure 2
Rev. SpA | Page 7 of 43
3.3 2.0 30 25 40
15
ADP3212/NCP3218
Parameter BST Quiescent Current LOW-SIDE MOSFET DRIVER Pull-up Resistance, Sourcing Current3 Pull-down Resistance, Sinking Current3 Transition Times Propagation Delay Times SW Transition Timeout SW Off Threshold PVCC Quiescent Current BOOTSTRAP RECTIFIER SWITCH On Resistance3
1 2
Symbol
Conditions EN = L (Shutdown) EN = H, no switching
Min
Typ 1 200 1.7 0.8
Max 10
Units A A ns ns ns ns V A A
2.8 1.7 35 35 30 350 10
trDRVL tfDRVL tpdhDRVL tTOSW VOFFSW
CL = 3 nF, Figure 2 CL = 3 nF, Figure 2 CL = 3 nF, Figure 2 DRVH = L, SW = 2.5 V EN = L (Shutdown) EN = H, no switching
100
15 14 11 250 2.5 1 170
EN = L or EN = H and DRVL = H
4
6
8
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not production tested. 3 Based on bench characterization data.
Rev. SpA | Page 8 of 43
ADP3212/NCP3218 TIMING DIAGRAM
Timing is referenced to the 90% and 10% points, unless otherwise noted.
IN tpdlDRVL DRVL tfDRVL tpdlDRVH trDRVL
tfDRVH tpdhDRVH trDRVH
DRVH (WITH RESPECT TO SW)
VTH
VTH
tpdhDRVL SW 1V
06374-006
Figure 2. Timing Diagram
Rev. SpA | Page 9 of 43
ADP3212/NCP3218 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC, PVCC1, PVCC2 FBRTN, PGND1, PGND2 BST1, BST2, DRVH1, DRVH2 DC t < 200 ns BST1 to PVCC, BST2 to PVCC DC t < 200 ns BST1 to SW1, BST2 to SW2 SW1, SW2 DC t < 200 ns DRVH1 to SW1, DRVH2 to SW2, DRVL1 to PGND1, DRVL2 to PGND2 DC t < 200 ns RAMP (in Shutdown) All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (JA) 2-Layer Board Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating -0.3 V to +6 V -0.3 V to +0.3 V -0.3 V to +28 V -0.3 V to +33 V -0.3 V to +22 V -0.3 V to +28 V -0.3 V to +6 V -1 V to +22 V -6 V to +28 V -0.3 V to +6 V -0.3 V to +6 V -5 V to +6 V -0.3 V to +22 V -0.3 V to +6 V -65C to +150C -40C to 100C 125C 30.5C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. SpA | Page 10 of 43
ADP3212/NCP3218 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VID0 VID1 VID2 VID3 VID4 VID5 VID6 PSI DPRSLP PH0 PH1 VCC
Figure 3. QFN Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic EN PWRGD IMON CLKEN FBRTN FB COMP TRDET Description Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTT low, and pulls CLKEN high. Power-Good Output. Open-drain output. A low logic state means that the output voltage is outside of the VID DAC defined range. Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to FBRTN sets the current monitor gain. Clock Enable Output. Open-drain output. A low logic state enables the CPU internal PLL clock to lock to the external clock. Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the ground return for the VID DAC and the voltage error amplifier blocks. Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier. Voltage Error Amplifier Output and Frequency Compensation Point. Transient Detect Output. This pin is pulled low when a load release transient is detected. During repetitive load transients at high frequencies, this circuit optimally positions the maximum and minimum output voltage into a specified loadline window. Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code. Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator temperature at the remote sensing point exceeded a set alarm threshold level. Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling function and disables the crowbar, or overvoltage protection (OVP), feature of the chip. Analog and Digital Signal Ground. This pin sets the internal bias currents. A 80kohm resistor is connected from this pin to ground. RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn-on threshold voltage. Multiphase Frequency Setting Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device when operating in multiphase PWM mode.threshold of the converter.
9 10 11
VARFREQ VRTT TTSNS
12 13 14 15
GND IREF RPM RT
IREF RPM RT RAMP LLINE CSREF CSSUM CSCOMP ILIM OD3 PWM3 SWFB3
Rev. SpA | Page 11 of 43
ADP3212/NCP3218
Pin No. 16 17 18 Mnemonic RAMP LLINE CSREF Description PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets the slope of the internal PWM stabilizing ramp used for phase-current balancing. Output Load Line Programming Input. The center point of a resistor divider between CSREF and CSCOMP is connected to this pin to set the load line slope. Current Sense Reference Input. This pin must be connected to the common point of the output inductors. The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop transient control of the converter output voltage. Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor currents to provide total current information. Current-Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the current-sense amplifier and the positioning loop response time. Current-Limit Setpoint. An external resistor from this pin to CSCOMP sets the current-limit threshold of the converter. Multiphase Output Disable Logic Output. This pin is actively pulled low when the ADP3212/NCP3218 enters single-phase mode or during shutdown. Connect this pin to the SD inputs of the Phase-3 MOSFET drivers. Logic-Level PWM Output for phase 3. Connect to the input of an external MOSFET driver such as the ADP3611. Current Balance Input for phase 3. Input for measuring the current level in phase 3. SWFB3 should be left open for 1 or 2 phase configuration. High-Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage while the high-side MOSFET is on. High-Side Gate Drive Output for Phase 2. Current Return for High-Side Gate Drive for phase 2. Current Balance Input for phase 2. Input for measuring the current level in phase 2. SWFB2 should be left open for 1 phase configuration. Low-Side Gate Drive Output for Phase 2. Low-Side Driver Power Ground Low-Side Gate Drive Output for Phase 1.. Power Supply Input/Output of Low-Side Gate Drivers. Current Balance Input for phase 1. Input for measuring the current level in phase 1. Current Return For High-Side Gate Drive for phase 1. High-Side Gate Drive Output for Phase 1. High-Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage while the high-side MOSFET is on. Power Supply Input/Output of the Controller. Phase Number Configuration Input. Connect to VCC for 3 phase configuration. Phase Number Configuration Input. Connect to GND for 1 phase configuration. Connect to VCC for multiphase configuration. Deeper Sleep Control Input. Power State Indicator Input. Pulling this pin to GND forces the ADP3212/NCP3218 to operate in single-phase mode. Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3 V to 1.5 V (see Table 6).
19 20 21 22
CSSUM CSCOMP ILIM OD3
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 to 48
PWM3 SWFB3 BST2 DRVH2 SW2 SWFB2 DRVL2 PGND DRVL1 PVCC SWFB1 SW1 DRVH1 BST1 VCC PH1 PH0 DPRSLP PSI VID6 to VID0
Rev. SpA | Page 12 of 43
ADP3212/NCP3218 TEST CIRCUITS
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PSI#
PH1
DPRSLP
PH2 PWM3
CSCOMP
CSSUM
SWFB3
CSREF
RAMP
LLINE
OD3#
IREF
RPM
ILIM
RT
VCC
Figure 6. Positioning Accuracy Figure 4. Closed-Loop Output Voltage Accuracy
5V 37 20 39k 1k 1.0V 12 100nF 19 18
VCC
ADP3212
CSCOMP CSSUM CSREF GND V os =
+ CSCOMP - 1V 40V
Figure 5. Current Sense Amplifier, VOS
Rev. SpA | Page 13 of 43
ADP3212/NCP3218 TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20C to 100C, unless otherwise noted.
PER PHASE SWITCHING FREQUENCY (kHz)
400 350 300 250 200 150 100 50 0 0.25
1000 Switching Frequency (kHz)
VARFREQ = 0V
VID = 1.4125V
VID = 1.2125V
VARFREQ = 5V
VID = 1.1V
RT = 187k 2 Phase Mode
0.5 0.75 1 1.25 1.5
VID = 0.8125 100 10 VID = 0.6125 100 Rt RESISTANCE (k) 1000
VID OUTPUT VOLTAGE (V)
Figure 7. Switching Frequency vs. VID Output Voltage in PWM Mode
Figure 8. Per Phase Switching Frequency vs. RT Resistance
Rev. SpA | Page 14 of 43
ADP3212/NCP3218 THEORY OF OPERATION
The ADP3212/NCP3218 combines multimode pulse-widthmodulated (PWM) control and ramp-pulse-modulated (RPM) control with multiphase logic outputs for use in single-, dualphase, or triple-phase synchronous buck CPU core supply power converters. The internal 7-bit VID DAC conforms to the Intel IMVP-6.5 specifications. Multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling high currents in a single-phase converter would put too high of a thermal stress on system components such as the inductors and MOSFETs. The multimode control of the ADP3212/NCP3218 is a stable, high performance architecture that includes * * * * * * * * * * Current and thermal balance between phases High speed response at the lowest possible switching frequency and minimal count of output decoupling capacitors Minimized thermal switching losses due to lower frequency operation High accuracy load line regulation High current output by supporting 2-phase or 3-phase operation Reduced output ripple due to multiphase ripple cancellation High power conversion efficiency with heavy and light loads Increased immunity from noise introduced by PC board layout constraints Ease of use due to independent component selection Flexibility in design by allowing optimization for either low cost or high performance Table 4. Phase Number Configuration PH0 0 1 0 1 PH1 0 0 1 1 Number of Phases Configured 1 1 (GPU Mode) 2 3
In mulit-phase configuration, the timing relationship between the phases is determined by internal circuitry that monitors the PWM outputs. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be active at a time, permitting overlapping phases.
OPERATION MODES
The number of phases can be static (see the Number of Phases section) or dynamically controlled by system signals to optimize the power conversion efficiency with heavy and light loads. If ADP3212/NCP3218 is configured for mulit-phase configuration, during a VID transient or with a heavy load condition (indicated by DPRSLP being low and PSI being high), the ADP3212/NCP3218 runs in multi-phase, interleaved PWM mode to achieve minimal VCORE output voltage ripple and the best transient performance possible. If the load becomes light (indicated by PSI being low or DPRSLP being high), ADP3212/NCP3218 switches to single-phase mode to maximize the power conversion efficiency. In addition to changing the number of phases, the ADP3212/NCP3218 is also capable of dynamically changing the control method. In dual-phase operation, the ADP3212/NCP3218 runs in PWM mode, where the switching frequency is controlled by the master clock. In single-phase operation (commanded by the DPRSLP high state), the ADP3212/NCP3218 runs in RPM mode, where the switching frequency is controlled by the ripple voltage appearing on the COMP pin. In RPM mode, the DRVH1 pin is driven high each time the COMP pin voltage rises to a voltage limit set by the VID voltage and an external resistor connected between the RPM pin and GND. In RPM mode, the ADP3212/NCP3218 turns off the low-side (synchronous rectifier) MOSFET when the inductor current drops to 0. Turning off the low-side MOSFETs at the zero current crossing prevents reversed inductor current build up and breaks synchronous operation of
NUMBER OF PHASES
The number of operational phases can be set by the user. Tying the PH1 pin to the GND pin forces the chip into single-phase operation. Tying PH0 to GND and PH1 to VCC forces the chip into 2-phase operation. Tying PH0 and PH1 to VCC forces the chip in 3-phase operation. PH0 and PH1 should be hard wired to VCC or GND. The ADP3212/NCP3218 switches between single phase and multiphase operation with PSI and DPRSLP to optimize power conversion efficiency. Table 4 summarizes PH0 and PH1.
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ADP3212/NCP3218
high- and low-side switches. Due to the asynchronous operation, the switching frequency becomes slower as the load current decreases, resulting in good power conversion efficiency with very light loads. Table 5 summarizes how the ADP3212/NCP3218 dynamically changes the number of active phases and transitions the operation mode based on system signals and operating conditions.
GPU MODE
The ADP3212/NCP3218 can be used to power IMVP-6.5 GMCH. To configure the ADP3212/NCP3218 in GPU, connect PH1 to VCC and connect PH0 to GND. In GPU mode, the ADP3212/NCP3218 operates in single phase only. In GPU mode, the boot voltage is disabled. During start up, the output voltage ramps up to the programmed VID voltage. There is no other difference between GPU mode and normal CPU mode.
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ADP3212/NCP3218
Table 5. Phase Number and Operation Modes1
No. of Phases Selected by the User N [3,2 or 1] N [3,2 or 1] * N [3,2 or 1] * * No. of Phases in Operation N N 1 N 1 1
PSI No. * 1 0 0 * *
1 2
DPRSLP * 0 0 0 1 1
VID Transition2 Yes No No No No No
Current Limit * * No Yes No Yes
Operation Modes3 PWM, CCM only PWM, CCM only PWM, CCM only PWM, CCM only RPM, automatic CCM/DCM PWM, CCM only
* = don't care. VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient period is the same as that of PWRGD masking time. 3 CCM stands for continuous current mode, and DCM stands for discontinuous current mode.
Figure 9. Single-Phase RPM Mode Operation
ADP3212/NCP3218
I =A x I R R RAMP Clock Oscillator C + Flip-Flop S RD Q Gate Driver BST1 BST DRVH1 DRVH IN SW SW1 DRVL DRVL1 VCC RL L
R
D
I =A x I R R RAMP Clock Oscillator C + Flip-Flop S RD Q
R
A
D
I =A x I R R RAMP Clock Oscillator C + Flip-Flop S RD Q PWM3
R
A VCC
D
COMP
FB
+ FBRTN LLINE
+
CSCOMP
R
A C FB
CA CB
R
B
Figure 10. 3-Phase PWM Mode Operation
Rev. SpA | Page 18 of 43
+
+
RAMP
+ + + -
A
SWFB1 0.2V Gate Driver BST IN DRVH SW DRVL BST2 DRVH2 SW2 DRVL2
1 k
VCC RL L
SWFB2 0.2V
1 k
Gate Driver BST IN DRVH SW DRVL
VCC RL L LOAD
SWFB3 0.2V + _ + DAC _ R CSSUM R R CS PH PH PH
1 k
CSREF
R
C
CS
ADP3212/NCP3218
Setting Switch Frequency Master Clock Frequency in PWM Mode
When the ADP3212/NCP3218 runs in PWM, the clock frequency is set by an external resistor connected from the RT pin to GND. The frequency is constant at a given VID code but varies with the VID voltage: the lower the VID voltage, the lower the clock frequency. The variation of clock frequency with VID voltage maintains constant VCORE ripple and improves power conversion efficiency at lower VID voltages. Figure 8 shows the relationship between clock frequency and VID voltage, parameterized by RT resistance. To determine the switching frequency per phase, divide the clock by the number of phases in use. is an inherently more accurate method than detecting peak current or sampling the current across a sense element, such as the low-side MOSFET. The current sense amplifier can be configured several ways, depending on system optimization objectives, and the current information can be obtained by * * * Output inductor ESR sensing without the use of a thermistor for the lowest cost Output inductor ESR sensing with the use of a thermistor that tracks inductor temperature to improve accuracy Discrete resistor sensing for the highest accuracy
Switching Frequency in RPM Mode-- Single-Phase Operation
In single-phase RPM mode, the switching frequency is controlled by the ripple voltage on the COMP pin, rather than by the master clock. Each time the COMP pin voltage exceeds the RPM pin voltage threshold level determined by the VID voltage and the external resistor RPM resistor, an internal ramp signal is started and DRVH1 is driven high. The slew rate of the internal ramp is programmed by the current entering the RAMP pin. One-third of the RAMP current charges an internal ramp capacitor (5 pF typical) and creates a ramp. When the internal ramp signal intercepts the COMP voltage, the DRVH1 pin is reset low.
At the positive input of the CSA, the CSREF pin is connected to the output voltage. At the negative input (that is, the CSSUM pin of the CSA), signals from the sensing element (in the case of inductor DCR sensing, signals from the switch node side of the output inductors) are summed together by series summing resistors. The feedback resistor between the CSCOMP and CSSUM pins sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. The current information is then given as the voltage difference between the CSCOMP and CSREF pins. This signal is used internally as a differential input for the current limit comparator. An additional resistor divider connected between the CSCOMP and CSREF pins with the midpoint connected to the LLINE pin can be used to set the load line required by the microprocessor specification. The current information to set the load line is then given as the voltage difference between the LLINE and CSREF pins. This configuration allows the load line slope to be set independent from the current limit threshold. If the current limit threshold and load line do not have to be set independently, the resistor divider between the CSCOMP and CSREF pins can be omitted and the CSCOMP pin can be connected directly to LLINE. To disable voltage positioning entirely (that is, to set no load line), LLINE should be tied to CSREF. To provide the best accuracy for current sensing, the CSA has a low offset input voltage and the sensing gain is set by an external resistor ratio.
DIFFERENTIAL SENSING OF OUTPUT VOLTAGE
The ADP3212/NCP3218 combines differential sensing with a high accuracy VID DAC, referenced by a precision band gap source and a low offset error amplifier, to meet the rigorous accuracy requirement of the Intel IMVP-6.5 specification. In steady-state mode, the combination of the VID DAC and error amplifier maintain the output voltage for a worst-case scenario within 8 mV of the full operating output voltage and temperature range. The CPU core output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the positive regulation point--the VCC remote sensing pin of the microprocessor. FBRTN should be connected directly to the negative remote sensing point--the VSS sensing point of the CPU. The internal VID DAC and precision voltage reference are referenced to FBRTN and have a maximum current of 200 A for guaranteed accurate remote sensing.
ACTIVE IMPEDANCE CONTROL MODE
To control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between LLINE and CSREF, can be scaled to be equal to the required droop voltage. This droop voltage is calculated by multiplying the droop impedance of the regulator by the output current. This value is used as the control voltage of the PWM regulator. The droop voltage is subtracted from the DAC reference output voltage, and the resulting voltage is used as the voltage
OUTPUT CURRENT SENSING
The ADP3212/NCP3218 includes a dedicated current sense amplifier (CSA) to monitor the total output current of the converter for proper voltage positioning vs. load current and for over current detection. Sensing the current delivered to the load
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ADP3212/NCP3218
positioning setpoint. The arrangement results in an enhanced feedforward response.
VDC ADP3212 R SWFB1
33 SWFB1
Phase 1 Inductor
CURRENT CONTROL MODE AND THERMAL BALANCE
The ADP3212/NCP3218 has individual inputs for monitoring the current of each phase. The phase current information is combined with an internal ramp to create a current-balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. The current balance information is independent from the total inductor current information used for voltage positioning described in the Active Impedance Control Mode section. The magnitude of the internal ramp can be set so that the transient response of the system is optimal. The ADP3212/NCP3218 monitors the supply voltage to achieve feedforward control whenever the supply voltage changes. A resistor connected from the power input voltage rail to the RAMP pin determines the slope of the internal PWM ramp. More detail about programming the ramp is provided in the Application Information section. External resistors are placed in series with the SWFB1, SWFB2, and SWFB3 pins to create an intentional current imbalance. Such a condition can exist when one phase has better cooling and supports higher currents the other phases. Resistors RSWSB1, RSWFB2, and RSWFB3 (see figure 26) can be used to adjust thermal balance. It is recommended to add these resistors during the initial design to make sure placeholders are provided in the layout. To increase the current in any given phase, users should make RSWFB for that phase larger (that is, RSWFB = 1 k for the hottest phase and do not change it during balance optimization). Increasing RSWFB to 1.5 k makes a substantial increase in phase current. Increase each RSWFB value by small amounts to achieve thermal balance starting with the coolest phase. If adjusting current balance between phases is not needed, RSWFB should be 1 k for all phases.
VDC Phase 2 Inductor
R SWFB2
28
SWFB2
VDC R SWFB3
24
SWFB3
Phase 3 Inductor
Figure 11. Current Balance Resistors
VOLTAGE CONTROL MODE
A high-gain bandwidth error amplifier is used for the voltage mode control loop. The noninverting input voltage is set via the 7-bit VID DAC. The VID codes are listed in Table 6. The noninverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. The output of the error amplifier is the COMP pin, which sets the termination voltage of the internal PWM ramps. At the negative input, the FB pin is tied to the output sense location using RB, a resistor for sensing and controlling the output voltage at the remote sensing point. The main loop compensation is incorporated in the feedback network connected between the FB and COMP pins.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output that can be pulled up through an external resistor to a voltage rail-- not necessarily the same VCC voltage rail that is running the controller. A logic high level indicates that the output voltage is within the voltage limits defined by a range around the VID voltage setting. PWRGD goes low when the output voltage is outside of this range. Following the IMVP-6.5 specification, the PWRGD range is defined to be 300 mV less than and 200 mV greater than the actual VID DAC output voltage. For any DAC voltage less than 300 mV, only the upper limit of the PWRGD range is monitored. To prevent a false alarm, the power-good circuit is masked during various system transitions, including a VID change and entrance into or exit out of deeper sleep. The duration of the PWRGD mask is set to approximately 130 s by an internal timer. If the voltage drop is greater than 200 mV
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ADP3212/NCP3218
during deeper sleep entry or slow deeper sleep exit, the duration of PWRGD masking is extended by the internal logic circuit. When a VID input changes, the ADP3212/NCP3218 detects the change but ignores new code for a minimum of 400 ns. This delay is required to prevent the device from reacting to digital signal skew while the 7-bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and retriggers the internal PWRGD masking timer. As listed in Table 6, during a VID transient, the ADP3212/NCP3218 forces PWM mode regardless of the state of the system input signals. For example, this means that if the chip is configured as a dual-phase controller but is running in single-phase mode due to a light load condition, a current overload event causes the chip to switch to dual-phase mode to share the excessive load until the delayed current limit latch-off cycle terminates. In user-set single-phase mode, the ADP3212/NCP3218 usually runs in RPM mode. When a VID transition occurs, however, the ADP3212/NCP3218 switches to dual-phase PWM mode.
POWER-UP SEQUENCE AND SOFT START
The power-on ramp-up time of the output voltage is set internally. The ADP3212/NCP3218 steps sequentially through each VID code until it reaches the boot voltage. The power-up sequence, including the soft start is illustrated in Figure 12. After EN is asserted high, the soft start sequence starts. The core voltage ramps up linearly to the boot voltage. The ADP3212/NCP3218 regulates at the boot voltage for approximately 90s. After the boot time is over, CLKEN# is asserted low. Before CLKEN# is asserted low, the VID pins are ignored. 9ms after CLKEN# is asserted low, PWRGD is asserted high.
VCC = 5V EN VBOOT = 1.1V VCORE tBOOT CLKEN tCPU_PWRGD PWRGD
Figure 12. Power-Up Sequence of ADP3212/NCP3218
Light Load RPM DCM Operation
In single-phase normal mode, DPRSLP is pulled low and the APD3208 operates in continuous conduction mode (CCM) over the entire load range. The upper and lower MOSFETs run synchronously and in complementary phase. See Figure 13 for the typical waveforms of the ADP3212/NCP3218 running in CCM with a 7 A load current.
OUTPUT VOLTAGE 20mV/DIV
4
INDUCTOR CURRENT 5A/DIV
CURRENT LIMIT
The ADP3212/NCP3218 compares the differential output of a current sense amplifier to a programmable current limit setpoint to provide the current-limiting function. The current limit threshold is set by the user with a resistor connected from the ILIM pin to CSCOMP.
2
SWITCH NODE 5V/DIV
3
LOW-SIDE GATE DRIVE 5V/DIV
CHANGING VID ON THE FLY
The ADP3212/NCP3218 is designed to track dynamically changing VID code. As a consequence, the CPU VCC voltage can change without the need to reset the controller or the CPU. This concept is commonly referred to as VID on-the-fly (VID OTF) transient. A VID OTF can occur with either light or heavy load conditions. The processor alerts the controller that a VID change is occurring by changing the VID inputs in LSB incremental steps from the start code to the finish code. The change can be either upwards or downwards steps.
400ns/DIV
Figure 13. Single-Phase Waveforms in CCM
If DPRSLP is pulled high, the ADP3212/NCP3218 operates in RPM mode. If the load condition is light, the chip enters discontinuous conduction mode (DCM). Figure 14 shows a typical single-phase buck with one upper FET, one lower FET, an output inductor, an output capacitor, and a load resistor. Figure 15 shows the path of the inductor current with the upper FET on and the lower FET off. In Figure 16 the high-side FET is off and the low-side FET is on. In CCM, if one FET is on, its complementary FET must be off; however, in DCM, both high-
Rev. SpA | Page 21 of 43
06374-030
1
ADP3212/NCP3218
and low-side FETs are off and no current flows into the inductor (see Figure 17). Figure 18 shows the inductor current and switch node voltage in DCM. In DCM with a light load, the ADP3212/NCP3218 monitors the switch node voltage to determine when to turn off the low-side FET. Figure 19 shows a typical waveform in DCM with a 1 A load current. Between t1 and t2, the inductor current ramps down. The current flows through the source drain of the low-side FET and creates a voltage drop across the FET with a slightly negative switch node. As the inductor current ramps down to 0 A, the switch voltage approaches 0 V, as seen just before t2. When the switch voltage is approximately -6 mV, the low-side FET is turned off. Figure 18 shows a small, dampened ringing at t2. This is caused by the LC created from capacitance on the switch node, including the CDS of the FETs and the output inductor. This ringing is normal. The ADP3212/NCP3218 automatically goes into DCM with a light load. Figure 19 shows the typical DCM waveform of the ADP3212/NCP3218. As the load increases, the ADP3212/NCP3218 enters into CCM. In DCM, frequency decreases with load current. Figure 20 shows switching frequency vs. load current for a typical design. In DCM, switching frequency is a function of the inductor, load current, input voltage, and output voltage.
Q1 INPUT VOLTAGE DRVH SWITCH L NODE Q2 DRVL
06374-031
OFF L
Figure 17. Buck Topology Inductor Current During t2 and t3
INDUCTOR CURRENT
SWITCH NODE VOLTAGE
06374-034
OFF
C
LOAD
t0
t1
t2
t3
t4
Figure 18. Inductor Current and Switch Node in DCM
4
OUTPUT VOLTAGE
OUTPUT VOLTAGE 20mV/DIV
C
LOAD
SWITCH NODE 5V/DIV
2
Figure 14. Buck Topology
INDUCTOR CURRENT 5A/DIV
3
ON L
LOW-SIDE GATE DRIVE 5V/DIV 2s/DIV
06374-032
OFF
C
LOAD
Figure 19. Single-Phase Waveforms in DCM with 1 A Load Current
Figure 15. Buck Topology Inductor Current During t0 and t1
OFF L
Figure 16. Buck Topology Inductor Current During t1 and t2
06374-033
ON
C
LOAD
Rev. SpA | Page 22 of 43
06374-036
1
06374-035
ADP3212/NCP3218
400 350 300
FREQUENCY (kHz)
9V INPUT 250 19V INPUT 200 150 100
06374-037
50 0
0
2
4
6
8
10
12
14
LOAD CURRENT (A)
Figure 20. Single-Phase CCM/DCM Frequency vs. Load Current
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ADP3212/NCP3218
OUTPUT CROWBAR
To prevent the CPU and other external components from damage due to overvoltage, the ADP3212/NCP3218 turns off the DRVH1 and DRVH2 outputs and turns on the DRVL1 and DRVL2 outputs when the output voltage exceeds the OVP threshold (1.55 V typical). Turning on the low-side MOSFETs forces the output capacitor to discharge and the current to reverse due to current build up in the inductors. If the output overvoltage is due to a drainsource short of the high-side MOSFET, turning on the low-side MOSFET results in a crowbar across the input voltage rail. The crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the microprocessor from destruction. When the OVP feature is triggered, the ADP3212/NCP3218 is latched off. The latch-off function can be reset by removing and reapplying VCC to the ADP3212/NCP3218 or by briefly pulling the EN pin low. Pulling TTSNS to less than 1 V disables the overvoltage protection function. In this configuration, VRTT should be tied to ground. pin voltage drops to less than -300 mV, the low-side MOSFETs is turned off. DRVL outputs are allowed to turn back on when the CSREF voltage recovers to greater than -100 mV.
OUTPUT ENABLE AND UVLO
For the ADP3212/NCP3218 to begin switching, the VCC supply voltage to the controller must be greater than the VCCOK threshold and the EN pin must be driven high. If the VCC voltage is less than the VCCUVLO threshold or the EN pin is a logic low, the ADP3212/NCP3218 shuts off. In shutdown mode, the controller holds the PWM outputs low, shorts the capacitors of the SS and PGDELAY pins to ground, and drives the DRVH and DRVL outputs low. The user must adhere to proper power-supply sequencing during startup and shutdown of the ADP3212/NCP3218. All input pins must be at ground prior to removing or applying VCC, and all output pins should be left in high impedance state while VCC is off.
THERMAL THROTTLING CONTROL
The ADP3212/NCP3218 includes a thermal monitoring circuit to detect whether the temperature of the VR has exceeded a user-defined thermal throttling threshold. The thermal monitoring circuit requires an external resistor divider connected between the VCC pin and GND. The divider consists of an NTC thermistor and a resistor. To generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the TTSNS pin. An internal comparator circuit compares the TTSNS voltage to half the VCC threshold and outputs a logic level signal at the VRTT output when the temperature trips the user-set alarm threshold. The VRTT output is designed to drive an external transistor that in turn provides the high current, open-drain VRTT signal required by the IMVP-6.5 specification. The internal VRTT comparator has a hysteresis of approximately 100 mV to prevent high frequency oscillation of VRTT when the temperature approaches the set alarm point.
REVERSE VOLTAGE PROTECTION
Very large reverse current in inductors can cause negative VCORE voltage, which is harmful to the CPU and other output components. The ADP3212/NCP3218 provides a reverse voltage protection (RVP) function without additional system cost. The VCORE voltage is monitored through the CSREF pin. When the CSREF pin voltage drops to less than -300 mV, the ADP3212/NCP3218 triggers the RVP function by disabling all PWM outputs and driving DRVL1 and DRVL2 low, thus turning off all MOSFETs. The reverse inductor currents can be quickly reset to 0 by discharging the built-up energy in the inductor into the input dc voltage source via the forward-biased body diode of the high-side MOSFETs. The RVP function is terminated when the CSREF pin voltage returns to greater than -100 mV. Sometimes the crowbar feature inadvertently causes output reverse voltage because turning on the low-side MOSFETs results in a very large reverse inductor current. To prevent damage to the CPU caused from negative voltage, the ADP3212/NCP3218 maintains its RVP monitoring function even after OVP latch-off. During OVP latch-off, if the CSREF
OUTPUT CURRENT MONITOR
The ADP3212/NCP3218 has an output current monitor. The IMON pin sources a current proportional to the inductor current. A resistor from IMON pin to FBRTN sets the gain. A 0.1 F is added in parallel with RMON to filter the inductor ripple. The IMON pin is clamped to prevent it from going above 1.15V.
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ADP3212/NCP3218
Table 6. VID Codes
VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Output 1.5000 V 1.4875 V 1.4750 V 1.4625 V 1.4500 V 1.4375 V 1.4250 V 1.4125 V 1.4000 V 1.3875 V 1.3750 V 1.3625 V 1.3500 V 1.3375 V 1.3250 V 1.3125 V 1.3000 V 1.2875 V 1.2750 V 1.2625 V 1.2500 V 1.2375 V 1.2250 V 1.2125 V 1.2000 V 1.1875 V 1.1750 V 1.1625 V 1.1500 V 1.1375 V 1.1250 V 1.1125 V 1.1000 V 1.0875 V 1.0750 V 1.0625 V 1.0500 V 1.0375 V 1.0250 V 1.0125 V 1.0000 V 0.9875 V 0.9750 V 0.9625 V 0.9500 V 0.9375 V 0.9250 V 0.9125 V 0.9000 V 0.8875 V 0.8750 V 0.8625 V 0.8500 V 0.8375 V 0.8250 V 0.8125 V 0.8000 V VID6 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID3 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output 0.7875 V 0.7750 V 0.7625 V 0.7500 V 0.7375 V 0.7250 V 0.7125 V 0.7000 V 0.6875 V 0.6750 V 0.6625 V 0.6500 V 0.6375 V 0.6250 V 0.6125 V 0.6000 V 0.5875 V 0.5750 V 0.5625 V 0.5500 V 0.5375 V 0.5250 V 0.5125 V 0.5000 V 0.4875 V 0.4750 V 0.4625 V 0.4500 V 0.4375 V 0.4250 V 0.4125 V 0.4000 V 0.3875 V 0.3750 V 0.3625 V 0.3500 V 0.3375 V 0.3250 V 0.3125 V 0.3000 V 0.2875 V 0.2750 V 0.2625 V 0.2500 V 0.2375 V 0.2250 V 0.2125 V 0.2000 V 0.1875 V 0.1750 V 0.1625 V 0.1500 V 0.1375 V 0.1250 V 0.1125 V 0.1000 V 0.0875 V
ADP3212/NCP3218
VID6 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 1 VID2 0 0 1 1 1 1 0 VID1 1 1 0 0 1 1 0 VID0 0 1 0 1 0 1 0 Output 0.0750 V 0.0625 V 0.0500 V 0.0375 V 0.0250 V 0.0125 V 0.0000 V VID6 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 VID2 0 0 0 1 1 1 1 VID1 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 Output 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V
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ADP3212/NCP3218
Figure 21. Typical Dual-Phase Application Circuit
Rev. SpA | Page 27 of 43
ADP3212/NCP3218 APPLICATION INFORMATION
The design parameters for a typical IMVP-6.5-compliant CPU core VR application are as follows: * * * * * * * * * * * * Maximum input voltage (VINMAX) = 19 V Minimum input voltage (VINMIN) = 8 V Output voltage by VID setting (VVID) = 1.05 V Maximum output current (IO) = 52 A Droop resistance (RO) = 1.9 m Nominal output voltage at 40 A load (VOFL) = 0.9512 V Static output voltage drop from no load to full load (V) = VONL - VOFL = 1.05 V - 0.9512 V = 98 mV Maximum output current step (IO) = 52 A Number of phases (n) = 2 Switching frequency per phase (fSW) = 300 kHz Duty cycle at maximum input voltage (DMAX) = 0.13 V Duty cycle at minimum input voltage (DMIN) = 0.055 V
SETTING THE SWITCHING FREQUENCY FOR RPM OPERATION OF PHASE 1
During the RPM operation of Phase 1, the ADP3212/NCP3218 runs in pseudoconstant frequency if the load current is high enough for continuous current mode. While in DCM, the switching frequency is reduced with the load current in a linear manner.
To save power with light loads, lower switching frequency is usually preferred during RPM operation. However, the VCORE ripple specification of IMVP-6.5 sets a limitation for the lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM can be equal to, greater than, or less than its counterpart in PWM. A resistor from RPM to GND sets the pseudo constant frequency as following:
SETTING THE CLOCK FREQUENCY FOR PWM
In PWM operation, the ADP3212/NCP3218 uses a fixedfrequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. For a dual-phase design, a clock frequency of 600 kHz sets the switching frequency to 300 kHz per phase. This selection represents the trade-off between the switching losses and the minimum sizes of the output filter components. To achieve a 600 kHz oscillator frequency at a VID voltage of 1.2 V, RT must be 181 k. Alternatively, the value for RT can be calculated by using the following equation:
R RPM =
A x (1 - D ) x VVID 2 x RT xR - 0.5 k (3 VVID + 1.0 V R R x C R x f SW
)where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude.
SOFT START AND CURRENT LIMIT LATCH-OFF DELAY TIMES INDUCTOR SELECTION
The choice of inductance determines the ripple current of the inductor. Less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs. However, this allows the use of smaller-size inductors, and for a specified peak-to-peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. For a multiphase converter, the practical value for peak-to-peak inductor ripple current is less than 50% of the maximum dc current of that inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current. Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage.
RT =
VVID + 1V - 16k 2 x n x f SW x 9 pF
(1)
where: 9 pF and 16 k are internal IC component values. VVID is the VID voltage in volts. n is the number of phases. fSW is the switching frequency in hertz for each phase. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor. When VARFREQ pin is connected to ground, the switching frequency does not change with VID. The value for RT can be calculated by using the following equation.
RT =
1V - 16k n x 2 x f SW x 9 pF
(2)
IR =
Rev. SpA | Page 28 of 43
VVID x (1 - D MIN ) f SW x L
(4)
ADP3212/NCP3218
L VVID x RO x (1 - ( n x DMIN )) f SW x VRIPPLE
(5) The output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low-pass filter. The summing is implemented by the CS amplifier that is configured with resistor RPH(x) (summer) and resistors RCS and CCS (filters). The output resistance of the regulator is set by the following equations:
RO = RCS x R SENSE R PH ( x )
Solving Equation 5 for a 16 mV peak-to-peak output ripple voltage yields
L
1.05 V x 1.9 m x (1 - 2 x 0.055) = 528 nH 300 kHz x 16 mV
(6)
If the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. Choosing a 490 nH inductor is a good choice for a starting point, and it provides a calculated ripple current of 9.0 A. The inductor should not saturate at the peak current of 24.5 A, and it should be able to handle the sum of the power dissipation caused by the winding's average current (20 A) plus the ac core loss. In this example, 330 nH is used. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. Too large of a DCR causes excessive power losses, whereas too small of a value leads to increased measurement error. For this example, an inductor with a DCR of 0.8 m is used.
C CS =
L RSENSE x RCS
(7)
where RSENSE is the DCR of the output inductors. Either RCS or RPH(x) can be chosen for added flexibility. Due to the current drive ability of the CSCOMP pin, the RCS resistance should be greater than 100 k. For example, initially select RCS to be equal to 200 k, and then use Equation 7 to solve for CCS:
CCS = 330 nH 0.8 m x 200 k = 2.1 nF
If CCS is not a standard capacitance, RCS can be tuned. For example, if the optimal CCS capacitance is 1.5 nF, adjust RCS to 280 k. For best accuracy, CCS should be a 5% NPO capacitor. In this example, a 220 k is used for RCS to achieve optimal results.
Selecting a Standard Inductor
After the inductance and DCR are known, select a standard inductor that best meets the overall design goals. It is also important to specify the inductance and DCR tolerance to maintain the accuracy of the system. Using 20% tolerance for the inductance and 15% for the DCR at room temperature are reasonable values that most manufacturers can meet.
Next, solve for RPH(x) by rearranging Equation 6 as follows:
R PH ( x )
0.8 m 2.1 m
x 220 k = 83.8 k
The standard 1% resistor for RPH(x) is 86.6 k.
Inductor DCR Temperature Correction
If the DCR of the inductor is used as a sense element and copper wire is the source of the DCR, the temperature changes associated with the inductor's winding must be compensated for. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, series resistors RCS1 and RCS2 (see Figure 22) are needed to linearize the NTC and produce the desired temperature coefficient tracking.
Power Inductor Manufacturers
The following companies provide surface-mount power inductors optimized for high power applications upon request: * * * * Vishay Dale Electronics, Inc. (605) 665-9301 Panasonic (714) 373-7334 Sumida Electric Company (847) 545-6700 NEC Tokin Corporation (510) 324-4110
Output Droop Resistance
The design requires that the regulator output voltage measured at the CPU pins decreases when the output current increases. The specified voltage drop corresponds to the droop resistance (RO).
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3. Find the relative value of RCS required for each of the two temperatures. The relative value of RCS is based on the percentage of change needed, which is initially assumed to be 0.39%/C in this example. The relative values are called r1 (r1 is 1/(1+ TC x (T1 - 25))) and r2 (r2 is 1/(1 + TC x (T2 - 25))), where TC is 0.0039, T1 is 50C, and T2 is 90C. Compute the relative values for rCS1, rCS2, and rTH by using the following equations:
4.
Figure 22. Temperature-Compensation Circuit Values
The following procedure and expressions yield values for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value. 1. Select an NTC to be used based on its type and value. Because the value needed is not yet determined, start with a thermistor with a value close to RCS and an NTC with an initial tolerance of better than 5%. Find the relative resistance value of the NTC at two temperatures. The appropriate temperatures will depend on the type of NTC, but 50C and 90C have been shown to work well for most types of NTCs. The resistance values are called A (A is RTH(50C)/RTH(25C)) and B (B is RTH(90C)/RTH(25C)). Note that the relative value of the NTC is always 1 at 25C.
rCS2 =
rCS1 =
( A - B) x r1 x r2 - A x (1 - B) x r2 + B x (1 - A) x r1 (8) A x (1 - B) x r1 - B x (1 - A) x r2 - ( A - B)
(1 - A) 1 A - 1 - rCS2 r1 - rCS2 1 1 1 - 1 - rCS2 rCS1
rTH =
2.
5.
Calculate RTH = rTH x RCS, and then select a thermistor of the closest value available. In addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one:
k=
6.
RTH ( ACTUAL ) RTH (CALCULATED )
(9)
Calculate values for RCS1 and RCS2 by using the following equations:
R CS1 = RCS x k x rCS1
RCS2 = RCS x ((1 - k ) + (k x rCS2 ))
(10)
For example, if a thermistor value of 100 k is selected in Step 1, an available 0603-size thermistor with a value close to RCS is the Vishay NTHS0603N04 NTC thermistor, which has resistance values of A = 0.3359 and B = 0.0771. Using the equations in Step 4, rCS1 is 0.359, rCS2 is 0.729, and rTH is 1.094. Solving for rTH yields 241 k, so a thermistor of 220 k would be a reasonable selection, making k equal to 0.913. Finally, RCS1 and RCS2 are found to be 72.1 k and 166 k. Choosing the closest 1% resistor for RCS2 yields 165 k. To correct for this approximation, 73.3 k is used for RCS1.
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COUT SELECTION
The required output decoupling for processors and platforms is typically recommended by Intel. For systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement. Select the number of ceramics and determine the total ceramic capacitance (CZ). This is based on the number and type of capacitors used. Keep in mind that the best location to place ceramic capacitors is inside the socket; however, the physical limit is twenty 0805-size pieces inside the socket. Additional ceramic capacitors can be placed along the outer edge of the socket. A combined ceramic capacitor value of 200 F to 300 F is recommended and is usually composed of multiple 10 F or 22 F capacitors. Ensure that the total amount of bulk capacitance (CX) is within its limits. The upper limit is dependent on the VID on-the-fly output voltage stepping (voltage step, VV, in time, tV, with error of VERR); the lower limit is based on meeting the critical capacitance for load release at a given maximum load step, IO. The current version of the IMVP-6.5 specification allows a maximum VCORE overshoot (VOSMAX) of 10 mV more than the VID voltage for a step-off load current. For example, if 30 pieces of 10 F, 0805-size MLC capacitors (CZ = 300 F) are used, the fastest VID voltage change is when the device exits deeper sleep, during which the VCORE change is 220 mV in 22 s with a setting error of 10 mV. If k = 3.1, solving for the bulk capacitance yields
C X ( MIN )
330 nH x 27.9 A - 300 F = 1.0 mF 10 mV x 1.4375 V 2 x 2.1 m+ 27.9 A 330 nH x 220 mV 2 x 3.12 x (2.1 m) 2 x 1.4375 V x
C X ( MAX )
2 22 s x 1.4375 V x 2 x 3.1 x 2.1 m - 1 - 300 F 1+ 220 mV x 490 nH
= 21 mF Using six 330 F Panasonic SP capacitors with a typical ESR of 7 m each yields CX = 1.98 mF and RX = 1.2 m. Ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using
C X ( MIN )
L x I O VOSMAX n x RO + I O
V L xV 2 n x k 2 x RO VVID
x VVID
-CZ

2
LX CZ x RO2 x Q2
(11)
(13)
L X 300 F x (2.1 m )2 x 2 = 2 nH
where: Q is limited to the square root of 2 to ensure a critically damped system. LX is about 150 pH for the six SP capacitors, which is low enough to avoid ringing during a load change. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing. For this multimode control technique, an all ceramic capacitor design can be used if the conditions of Equations 11, 12, and 13 are satisfied.
C X ( MAX )
V n x k x RO x 1 + t v VID x V L V
- 1 - C Z
V where k = -ln ERR V V

(12)
To meet the conditions of these expressions and the transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is greater than CX(MAX), the system does not meet the VID on-the-fly and/or the deeper sleep exit specifications and may require less inductance or more phases. In addition, the switching frequency may have to be increased to maintain the output ripple.
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POWER MOSFETS
For typical 20 A per phase applications, the N-channel power MOSFETs are selected for two high-side switches and two or three low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). Because the voltage of the gate driver is 5 V, logiclevel threshold MOSFETs must be used. The maximum output current, IO, determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. In the ADP3212/NCP3218, currents are balanced between phases; the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO):
voltage that are being switched. Basing the switching speed on the rise and fall times of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET:
PS( MF ) = 2 x f SW x
VDC x I O n x RG x MF x C ISS n MF n
(15)
where: nMF is the total number of main MOSFETs. RG is the total gate resistance. CISS is the input capacitance of the main MOSFET. The most effective way to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following equation:
I PC ( MF ) = D x O n MF 1 nx I R + x 12 n MF
2
PSF
I = (1 - D) x O nSF
1 nx I R + x 12 n SF
2

2
x R DS( SF )
(14)

2
x R DS( MF )
(16)
where RDS(MF) is the on resistance of the MOSFET.
where: D is the duty cycle and is approximately the output voltage divided by the input voltage. IR is the inductor peak-to-peak ripple current and is approximately (1 - D ) x VOUT IR = L x f SW
Typically, a user wants the highest speed (low CISS) device for a main MOSFET, but such a device usually has higher on resistance. Therefore, the user must select a device that meets the total power dissipation (about 0.8 W to 1.0 W for an 8-lead SOIC) when combining the switching and conduction losses. For example, an IRF7821 device can be selected as the main MOSFET (four in total; that is, nMF = 4), with approximately CISS = 1010 pF (maximum) and RDS(MF) = 18 m (maximum at TJ = 120C), and an IR7832 device can be selected as the synchronous MOSFET (four in total; that is, nSF = 4), with RDS(SF) = 6.7 m (maximum at TJ = 120C). Solving for the power dissipation per MOSFET at IO = 40 A and IR = 9.0 A yields 630 mW for each synchronous MOSFET and 590 mW for each main MOSFET. A third synchronous MOSFET is an option to further increase the conversion efficiency and reduce thermal stress. Finally, consider the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation:
f PDRV = SW x (n MF x Q GMF + n SF x Q GSF ) + I CC x VCC 2xn
Knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required RDS(ON) for the MOSFET. For 8-lead SOIC or 8-lead SOICcompatible MOSFETs, the junction-to-ambient (PCB) thermal impedance is 50C/W. In the worst case, the PCB temperature is 70C to 80C during heavy load operation of the notebook, and a safe limit for PSF is about 0.8 W to 1.0 W at 120C junction temperature. Therefore, for this example (40 A maximum), the RDS(SF) per MOSFET is less than 8.5 m for two pieces of low-side MOSFETs. This RDS(SF) is also at a junction temperature of about 120C; therefore, the RDS(SF) per MOSFET should be less than 6 m at room temperature, or 8.5 m at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high. The high-side (main) MOSFET must be able to handle two main power dissipation components: conduction losses and switching losses. Switching loss is related to the time for the main MOSFET to turn on and off and to the current and
(17)
where QGMF is the total gate charge for each main MOSFET, and QGSF is the total gate charge for each synchronous MOSFET. The previous equation also shows the standby dissipation (ICC times the VCC) of the driver.
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ADP3212/NCP3218
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used to set the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Use the following expression to determine a starting value: where: RLIM is the current limit resistor. RO is the output load line. ILIM is the current limit setpoint. When the ADP3212/NCP3218 is configured for 3 phase operation, the equation above is used to set the current limit. When the ADP3212/NCP3218 switches from 3 phase to 1 phase operation by PSI or DPRSLP signal, the current is single phase is one third of the current limit in 3 phase. When the ADP3212/NCP3218 is configured for 2 phase operation, the equation above is used to set the current limit. When the ADP3212/NCP3218 switches from 2 phase to 1 phase operation by PSI or DPRSLP signal, the current is single phase is one half of the current limit in 2 phase. When the ADP3212/NCP3218 is configured for 1 phase operation, the equation above is used to set the current limit.
RR =
AR x L 3 x AD x RDS x C R
(18)
RR =
0.5 x 360 nH = 462 k 3 x 5 x 5.2 m x 5 pF
where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low-side MOSFET on resistance. CR is the internal ramp capacitor value. Another consideration in the selection of RR is the size of the internal ramp voltage (see Equation 19). For stability and noise immunity, keep the ramp size larger than 0.5 V. Taking this into consideration, the value of RR in this example is selected as 280 k. The internal ramp voltage magnitude can be calculated as follows:
CURRENT MONITOR
The ADP3212/NCP3218 has output current monitor. The IMON pin sources a current proportional to the total inductor current. A resistor, RMON, from IMON to FBRTN sets the gain of the output current monitor. A 0.1 F is placed in parallel with RMON to filter the inductor current ripple and high frequency load transients. Since the IMON pin is connected directly to the CPU, it is clamped to prevent it from going above 1.15V. The IMON pin current is equal to the RLIMtimes a fixed gain of 4. RMON can be found using the following equation:
VR =
AR x (1 - D ) x VVID RR x C R x f SW
(19)
VR =
0.5 x (1 - 0.061) x 1.150 V = 0.83 V 462 k x 5 pF x 280 kHz
RMON =
1.15V x RLIM 4 x RO x I FS
(28)
The size of the internal ramp can be increased or decreased. If it is increased, stability and transient response improves but thermal balance degrades. Conversely, if the ramp size is decreased, thermal balance improves but stability and transient response degrade. In the denominator of Equation 18, the factor of 3 sets the minimum ramp size that produces an optimal combination of good stability, transient response, and thermal balance.
where: RMON is the current monitor resistor. RMON is connected from IMON pin to FBRTN. RLIM is the current limit resistor. RO is the output load line resistance. IFS is the output current when the voltage on IMON is at full scale.
CURRENT LIMIT SETPOINT
To select the current limit setpoint, the resistor value for RCLIM must be determined. The current limit threshold for the ADP3212/NCP3218 is set with RCLIM. RCLIM can be found using the following equation:
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3212/NCP3218 allows the best possible response of the regulator's output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and that is equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load
RLIM =
I LIM x RO 60A
(20)
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ADP3212/NCP3218
current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling. With the multimode feedback structure of the ADP3212/NCP3218, it is necessary to set the feedback compensation so that the converter's output impedance works in parallel with the output decoupling. In addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter). A Type III compensator on the voltage feedback is adequate for proper compensation of the output filter. Figure 23 shows the Type III amplifier used in the ADP3212/NCP3218. Figure 24 shows the locations of the two poles and two zeros created by this amplifier.
f P0 =
1 2 (C A + C B ) x RFB
(23)
f P1 =
C A + CB 2 x RA x C B x C A
(24)
The expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for 12 section):
R E = n x R O + A D x R DS + R L x V RT VVID +
(25)
2 x L x (1 - (n x D)) x V RT n x C X x R O x VVID TA = C X x (RO - R' ) + L X RO - R' x RO RX
(26) (27)
TB = (R X + R'- RO )x C X
A x RDS VRT x L - D 2 x f SW TC = VVID x RE
(28)
TD =
Figure 23. Voltage Error Amplifier
2 C X x C Z x RO C X x (R O - R ' ) + C Z x R O
(29)
where: R' is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.4 m (assuming an 8-layer motherboard). RDS is the total low-side MOSFET for on resistance per phase. AD is 5. VRT is 1.25 V. LX is 150 pH for the six Panasonic SP capacitors.
Figure 24. Poles and Zeros of Voltage Error Amplifier
The following equations give the locations of the poles and zeros shown in Figure 24:
f Z1 =
f Z2 =
1 2 x C A x R A
1
(21)
2 x C FB x R FB
(22)
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ADP3212/NCP3218
The compensation values can be calculated as follows:
n x RO x TA CA = RE x RB
RA = TC CA
RSnubber =
(30)
1 2 x x f Ringing x COSS 1
(35)
C Snubber =
(31)
x f Ringing x RSnubber
(36)
T CB = B RB
C FB = TD RA
2 PSnubber = C Snubber x VInput x f Swithing
(37)
(32) (33)
The standard values for these components are subject to the tuning procedure described in the Tuning Procedure for 12 section.
CIN SELECTION AND INPUT CURRENT di/dt REDUCTION
In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude that is one-nth of the maximum output current. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum rms current. The maximum rms capacitor current occurs at the lowest input voltage and is given by
Where RSnubber is the snubber resistor. CSnubber is the snubber capacitor. fRininging is the frequency of the ringing on the switch node when the high side MOSFET turns on. COSS is the low side MOSFET output capacitance at VInput. This is taken from the low side MOSFET data sheet. Vinput is the input voltage. fSwitching is the switching frequency. PSnubber is the power dissipated in RSnubber.
SELECTING THERMAL MONITOR COMPONENTS
To monitor the temperature of a single-point hot spot, set RTTSET1 equal to the NTC thermistor's resistance at the alarm temperature. For example, if the alarm temperature for VRTT is 100C and a Vishey thermistor (NTHS-0603N011003J) with a resistance of 100 k at 25C, or 6.8 k at 100C, is used, the user can set RTTSET1 equal to 6.8 k (the RTH1 at 100C).
I CRMS = D x I O x
1 -1 nx D
1 - 1 = 9.6 A 2 x 0.18
(34)
I CRMS = 0.18 x 40 A x
where IO is the output current. In a typical notebook system, the battery rail decoupling is achieved by using MLC capacitors or a mixture of MLC capacitors and bulk capacitors. In this example, the input capacitor bank is formed by eight pieces of 10 F, 25 V MLC capacitors, with a ripple current rating of about 1.5 A each.
Figure 25. Single-Point Thermal Monitoring
RC SNUBBER
It is important in any buck topology to use a resistor-capacitor snubber across the low side power MOSFET. The RC snubber dampens ringing on the switch node when the high side MOSFET turns on. The switch node ringing could cause EMI system failures and increased stress on the power components and controller. The RC snubber should be placed as close as possible to the low side MOSFET. Typical values for the resistor range from 1 to 10 . Typical values for the capacitor range from 330 pF to 4.7 nF. The exact value of the RC snubber depends on the PCB layout and MOSFET selection. Some fine tuning must be done to find the best values. The equation below is used to find the starting values for the RC subber.
To monitor the temperature of multiple-point hot spots, use the configuration shown in Figure 26. If any of the monitored hot spots reaches the alarm temperature, the VRTT signal is asserted. The following calculation sets the alarm temperature:
VFD VREF = x RTH1AlarmTemperature V 1 / 2 - FD VREF 1/ 2 +
RTTSET1
(38)
where VFD is the forward drop voltage of the parallel diode. Because the forward current is very small, the forward drop voltage is very low, that is, less than 100 mV. Assuming the same
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conditions used for the single-point thermal monitoring example--that is, an alarm temperature of 100C and use of an NTHS-0603N011003J Vishay thermistor--solving Equation 42 gives a RTTSET of 7.37 k, and the closest standard resistor is 7.32 k (1%). 6. Repeat Steps 4 and 5 until no adjustment of RPH is needed. Once this is achieved, do not change RPH, RCS1, RCS2, or RTH for the rest of the procedure. Measure the output ripple with no load and with a full load with scope, making sure both are within the specifications.
7.
Set the AC Load Line
1. 2. 3. 4.
Figure 26. Multiple-Point Thermal Monitoring
The number of hot spots monitored is not limited. The alarm temperature of each hot spot can be individually set by using different values for RTTSET1, RTTSET2, ... RTTSETn.
5.
TUNING PROCEDURE FOR ADP3212/NCP3218
Set Up and Test the Circuit
1. 2. 3. 4. Build a circuit based on the compensation values computed from the design spreadsheet. Connect a dc load to the circuit. Turn on the ADP3212/NCP3218 and verify that it operates properly. Check for jitter with no load and full load conditions.
Remove the dc load from the circuit and connect a dynamic load. Connect the scope to the output voltage and set it to dc coupling mode with a time scale of 100 s/div. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. Measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). Try to use a vertical scale of 100 mV/div or finer. The resulting waveform will be similar to that shown in Figure 27. Use the horizontal cursors to measure VACDRP and VDCDRP, as shown in Figure 27. Do not measure the undershoot or overshoot that occurs immediately after the step.
VACDRP VDCDRP
Set the DC Load Line
06374-046
1. 2.
Measure the output voltage with no load (VNL) and verify that this voltage is within the specified tolerance range. Measure the output voltage with a full load when the device is cold (VFLCOLD). Allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (VFLHOT). If the difference between the two measured voltages is more than a few millivolts, adjust RCS2 using Equation 39.
Figure 27. AC Load Line Waveform
6.
R CS2(NEW) = RCS2(OLD) x
3. 4.
V NL - V FLCOLD V NL - V FLHOT
(39)
If the difference between VACDRP and VDCDRP is more than a couple of millivolts, use Equation 46 to adjust CCS. It may be necessary to try several parallel values to obtain an adequate one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason).
5.
Repeat Step 2 until no adjustment of RCS2 is needed. Compare the output voltage with no load to that with a full load using 5 A steps. Compute the load line slope for each change and then find the average to determine the overall load line slope (ROMEAS). If the difference between ROMEAS and RO is more than 0.05 m, use the following equation to adjust the RPH values:
C CS ( NEW ) = C CS (OLD ) x
7.
V ACDRP VDCDRP
(41)
8.
R PH ( NEW ) = R PH (OLD ) x
R OMEAS RO
(40) 9.
Repeat Steps 5 and 6 until no adjustment of CCS is needed. Once this is achieved, do not change CCS for the rest of the procedure. Set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning VACDRP and VDCDRP are equal. Ensure that the load step slew rate and the power-up slew rate are set to ~150 A/s to 250 A/s (for example, a load
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ADP3212/NCP3218
step of 50 A should take 200 ns to 300 ns) with no overshoot. Some dynamic loads have an excessive overshoot at power-up if a minimum current is incorrectly set (this is an issue if a VTT tool is in use).
VTRANREL
VDROOP
Set the Initial Transient
1. With the dynamic load set at its maximum step size, expand the scope time scale to 2 s/div to 5 s/div. This results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after VDROOP (see Figure 28).
Figure 29. Transient Setting Waveform, Load Release
LAYOUT AND COMPONENT PLACEMENT
VDROOP
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
General Recommendations
1.
VTRAN1 VTRAN2
06374-047
Figure 28. Transient Setting Waveform, Load Step
2.
3.
If both overshoots are larger than desired, try the following adjustments in the order shown. a. Increase the resistance of the ramp resistor (RRAMP) by 25%. b. For VTRAN1, increase CB or increase the switching frequency. c. For VTRAN2, increase RA by 25% and decrease CA by 25%. If these adjustments do not change the response, it is because the system is limited by the output decoupling. Check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable. For load release (see Figure 29), if VTRANREL is larger than the value specified by IMVP-6.5, a greater percentage of output capacitance is needed. Either increase the capacitance directly or decrease the inductor values. (If inductors are changed, however, it will be necessary to redesign the circuit using the information from the spreadsheet and to repeat all tuning guide procedures).
2.
3.
4.
5.
6.
For best results, use a PCB of four or more layers. This should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 m at room temperature. When high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3212/NCP3218) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise. An analog ground plane should be used around and under the ADP3212/NCP3218 for referencing the components associated with the controller. This plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane. The components around the ADP3212/NCP3218 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are those to the FB and CSSUM pins. Refer to Figure 22 for more details on the layout for the CSSUM node. The output capacitors should be connected as close as possible to the load (or connector) that receives the power (for example, a microprocessor core). If the load is distributed,
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06374-048
ADP3212/NCP3218
the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic. Avoid crossing signal lines over the switching power path loop, as described in the Power Circuitry section. Connect a 1 F decoupling ceramic capacitor from VCC to GND. Place this capacitor as close as possible to the controller. Connect a 4.7 F decoupling ceramic capacitor from PVCC to PGND. Place capacitor as close as possible to the controller. opposite side of the PCB, where a plane can more readily transfer heat to the surrounding air. To achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the MOSFETs on the opposite side of the PCB. In addition, improvements in thermal performance can be obtained using the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers and extended under all power components.
7. 8.
3.
Power Circuitry
1. The switching power path on the PCB should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power-converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. When a power-dissipating component (for example, a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the
4.
Signal Circuitry
1. The output voltage is sensed and regulated between the FB and FBRTN pins, and the traces of these pins should be connected to the signal ground of the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be as small as possible. Therefore, the FB and FBRTN traces should be routed adjacent to each other, atop the power ground plane, and back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be Kelvin connected to the center point of the copper bar, which is the VCORE common node for the inductors of all the phases. On the back of the ADP3212/NCP3218 package, there is a metal pad that can be used to heat sink the device. Therefore, running vias under the ADP3212/NCP3218 is not recommended because the metal pad may cause shorting between vias.
2.
2.
3.
Rev. SpA | Page 38 of 43
ADP3212/NCP3218 OUTLINE DIMENSION
Figure 30. NCP3218 48-Lead Lead Frame Chip Scale Package [QFN_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters
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ADP3212/NCP3218
Figure 31. ADP3212 48-Lead Lead Frame Chip Scale Package [QFN_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters
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ADP3212/NCP3218
ORDERING GUIDE
Model ADP3212MNR2G1 NCP3218MNR2G1 Temperature Range -40C to 100C -40C to 100C Package Description 48-Lead Lead Frame Chip Scale Package [QFN_VQ] 7x7 mm, 0.5 mm pitch 48-Lead Lead Frame Chip Scale Package [QFN_VQ] 6x6 mm, 0.4 mm pitch Package Option CP-48-1 CP-48-1 Package Marking Line 1: ADP3212 Line 2: AWLYYWWG Line 1: NCP3218 Line 2: AWLYYWWG Ordering Quantity 2,500 2,500
1
G = RoHS Compliant Part.S
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ADP3212/NCP3218 NOTES
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ADP3212/NCP3218 NOTES
Rev. SpA | Page 43 of 43

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